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coreabc v3.1 handbook
actel corporation, mountain view, ca 94043 ? 2010 actel corporation. all rights reserved. printed in the united states of america part number: 50200085-5 release: september 2010 no part of this document may be copied or reproduced in any form or by any mean s without prior written consent of actel. actel makes no warranties with respect to this documentation and disclaims any implied warranties of merchant ability or fitness for a particular purpose. information in th is document is subject to ch ange without notice. actel assumes no responsibility for any errors that may appear in this document. this document contains confidential proprie tary information that is not to be disc losed to any unauthorized person without prio r written consent of actel corporation. trademarks actel, actel fusion, igloo, libe ro, pigeon point, proasic, smartf usion and the associated logos are trademarks or registered trademarks of actel corporation. all ot her trademarks and service marks are th e property of their respective owners.
coreabc v3.1 3 table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 coreabc overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 supported device families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 core version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 supported interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 supported tool flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 utilization and performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 internal architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 tool flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 smartdesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 simulation flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 synthesis in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 place-and-route in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 coreabc interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 overview of interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 en_datam parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 coreabc programmer?s model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 coreabc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 acm lookup table for use with coreai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 coreabc configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 configurable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 cross-validation of configuration fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 nvm data width on afs090 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 coreabc programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 coreabc instruction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 testbench and simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 unit testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 system simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
table of contents simulation logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9 example design using coreabc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 create a new project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 create a smartdesign design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 instantiate, configure, and connect the co mponents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 system simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 simulation of coreabc only (unit test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 place-and-route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10 coreabc v2.3 migration guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 a example instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 b instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 c list of document changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 d product support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 customer service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 actel customer techni cal support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 actel technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 contacting the customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5 introduction coreabc overview coreabc (abc = apb bus controller) is a simple, configurable, low gate count, programmable state machine/controller primarily targeted toward the impl ementation of advanced micr ocontroller bus architecture (amba ? ) advanced peripheral bus (apb) based designs. it is particularly suitable in the following situations: ? a programmable controller is required but a fu ll featured cpu such as core8051s or arm ? cortex?-m1 is not needed or cannot be justified due to cost or resour ce/size constraints. ? a full featured cpu based system requires a co reabc based programmable of fload engine/coprocessor subsystem for performance reasons. ? an actel fusion ? system using coreai or corepwm, for ex ample, requires programmable control either as a standalone design or as a fusion analog offload engine/coproc essor for a larger cpu based system. coreabc supports a comprehensive assemb ler based configurable instruction set architecture and extensive and flexible configuration of si ze and feature options, allowing it to be tu ned to meet the resource constraints and processing power requirements of a wide variety of applications. coreabc supports three program storage modes: ? hard mode: program image is stored in an in ternal rom implemented in fpga fabric tiles ? soft mode: program image is stored in actel fpga ram blocks which are initialized at runtime from the binary image stored in fusion nv m or an external flash memory ? nvm mode (fusion only): program image stored in and executed directly from fusion nvm coreabc is available through the actel libero ? integrated design environment (ide) ip catalog, through which it can be downloaded from a remote web- based repository and installed into the user's local vault, ready for use. it operates natively within the smartd esign design entry environment, allo wing it to be easily instantiated, configured, and connected to other ip core instances and generated ready for simulation, synthesis, etc. coreabc is an amba3 apb master which can connect to and mana ge any apb slave periphera ls via an amba3 apb bus fabric component such as coreapb3. figure 1 shows a coreabc based system that can monitor analog inputs, adjust output levels, and report status via an rs-232 link using coreuart. figure 1 ? typical coreabc system coreabc parallel i/o out parallel i/o in apb bus coreai corepwm coreuart
introduction 6 supported device families fusion igloo ? iglooe igloo plus proasic ? 3l proasic3 proasic3e proasic plus axcelerator? rtax-s core version this handbook supports coreabc v3.0. supported interfaces coreabc has an amba3 apb master interface, which is described in "coreabc interfaces" on page 15 . when configured in nvm mode, an additional amba3 apb slave interface is available for accessing the nvm block used to store instructions wi thin coreabc. apb access to the in struction nvm block may be used, for example, to maintain a nonvolatile l og of data values in cases where only one nvm block is available for coreabc's use. when configured in soft mode, an in itialization and configuration (initcfg) interface is used for initializing the ram blocks used for core abc's instruction memory. supported tool flows coreabc requires actel libero ide v8 .6 sp1 or later. additionally, verilog users must use synplicity ? v8.6.1 or later, which is downloadable from www.synplicity.com . utilization and performance coreabc utilization va ries depending on how it is configured. table 1 below and table 2 on page 9 provide typical utilization data for a ra nge of devices and data widths. the other conf iguration options for the core are collectively grouped to give three different corea bc configurations named sm all, medium, and large; these configurations are listed in table 3-1 on page 15 . coreabc can be implemented in several actel fpga devices. table 1 ? coreabc utilization data (hard mo de?instructions held in tiles) family data width config. comb. seq. ram total device utilization frequency mhz* fusion proasic?3/e igloo?/e 8 small 179 46 0 225 afs600 a3p600 agl600 1.6% 92 proasic plus 8 small 195 51 0 246 apa450 2.0% 81 axcelerator? rtax-s 8 small 96 45 0 141 ax250 rtax250 3.3% 123 note: *the frequency given in the table does not apply to the igloo devices. igloo family devices will run significantly slower than th e speed listed in the table.
utilization and performance 7 fusion proasic3/e igloo/e 16 small 238 59 0 297 afs600 a3p600 agl600 2.1% 79 proasic plus 16 small 269 63 0 332 apa450 2.7% 79 axcelerator rtax-s 16 small 127 57 0 184 ax250 rtax250 4.4% 98 fusion proasic3/e igloo/e 32 small 319 74 0 393 afs600 a3p600 agl600 2.8% 58 proasic plus 32 small 381 84 0 465 apa450 3.9% 60 axcelerator rtax-s 32 small 192 78 0 270 ax250 rtax250 6.4% 97 fusion proasic3/e igloo/e 8 medium 363 76 1 439 afs600 a3p600 agl600 3.2% 55 proasic plus 8 medium 439 88 1 527 apa450 4.3% 41 axcelerator rtax-s 8 medium 229 76 1 305 ax250 rtax250 7.2% 86 fusion proasic3/e igloo/e 16 medium 558 88 1 646 afs600 a3p600 agl600 4.7% 41 proasic plus 16 medium 630 95 2 725 apa450 5.9% 32 axcelerator rtax-s 16 medium 307 92 1 399 ax250 rtax250 9.4% 73 fusion proasic3/e igloo/e 32 medium 896 104 2 1,000 afs600 a3p600 agl600 7.2% 37 proasic plus 32 medium 947 112 4 1,059 apa450 8.6% 28 axcelerator rtax-s 32 medium 442 108 2 550 ax250 rtax250 13.0% 64 fusion proasic3/e igloo/e 8 large 474 82 1 556 afs600 a3p600 agl600 4.0% 42 proasic plus 8 large 565 94 1 659 apa450 5.4% 38 axcelerator rtax-s 8 large 291 86 1 377 ax250 rtax250 8.9% 71 fusion proasic3/e igloo/e 16 large 648 94 1 742 afs600 a3p600 agl600 5.4% 27 proasic plus 16 large 763 105 2 868 apa450 7.1% 24 table 1 ? coreabc utilization data (hard mode?ins tructions held in tiles) (continued) family data width config. comb. seq. ram total device utilization frequency mhz* note: *the frequency given in the table does not apply to the igloo devices. igloo family devices will run significantly slower than th e speed listed in the table.
introduction 8 axcelerator rtax-s 16 large 399 98 1 497 ax250 rtax250 11.8% 69 fusion proasic3/e igloo/e 32 large 1,014 111 2 1,125 afs600 a3p600 agl600 8.1% 34 proasic plus 32 large 1,082 126 4 1,208 apa450 9.8% 18 axcelerator rtax-s 32 large 586 119 2 705 ax250 rtax250 16.7% 53 table 1 ? coreabc utilization data (hard mode?ins tructions held in tiles) (continued) family data width config. comb. seq. ram total device utilization frequency mhz* note: *the frequency given in the table does not apply to the igloo devices. igloo family devices will run significantly slower than th e speed listed in the table.
utilization and performance 9 table 2 ? coreabc utilization data (soft mode?instructions held in ram) family data width config. comb. seq. ram total device utilization frequency mhz* fusion proasic3/e igloo/e 8 small 126 27 3 153 afs600 a3p600 agl600 1.1% 68 proasic plus 8 small 137 30 6 167 apa450 1.4% 53 axcelerator rtax-s 8 small 61 27 3 88 ax250 rtax250 2.1% 95 fusion proasic3/e igloo/e 16 small 179 36 4 215 afs600 a3p600 agl600 1.6% 67 proasic plus 16 small 213 41 8 254 apa450 2.1% 50 axcelerator rtax-s 16 small 94 35 4 129 ax250 rtax250 3.1% 84 fusion proasic3/e igloo/e 32 small 353 53 5 406 afs600 a3p600 agl600 2.9% 46 proasic plus 32 small 359 58 10 417 apa450 3.4% 42 axcelerator rtax-s 32 small 155 52 5 207 ax250 rtax250 4.9% 65 fusion proasic3/e igloo/e 8 medium 326 56 4 382 afs600 a3p600 agl600 2.8% 46 proasic plus 8 medium 409 59 7 468 apa450 3.8% 34 axcelerator rtax-s 8 medium 210 55 4 265 ax250 rtax250 6.3% 59 fusion proasic3/e igloo/e 16 medium 548 64 5 612 afs600 a3p600 agl600 4.4% 40 proasic plus 16 medium 659 73 10 732 apa450 6.0% 28 axcelerator rtax-s 16 medium 271 64 5 335 ax250 rtax250 7.9% 58 fusion proasic3/e igloo/e 32 medium 851 80 8 931 afs600 a3p600 agl600 6.7% 32 proasic plus 32 medium 892 96 16 988 apa450 8.0% 26 axcelerator rtax-s 32 medium 399 80 8 479 ax250 rtax250 11.3% 50 fusion proasic3/e igloo/e 8 large 462 62 5 524 afs600 a3p600 agl600 3.8% 40 note: *the frequency given in the table does not apply to the igloo devices. igloo fa mily devices will run significantly slower than the speed listed in the table.
introduction 10 proasic plus 8 large 534 67 9 601 apa450 4.9% 31 axcelerator rtax-s 8 large 282 61 5 343 ax250 rtax250 8.1% 63 fusion proasic3/e igloo/e 16 large 626 71 6 697 afs600 a3p600 agl600 5.0% 25 proasic plus 16 large 732 83 12 815 apa450 6.6% 21 axcelerator rtax-s 16 large 380 70 6 450 ax250 rtax250 10.7% 56 fusion proasic3/e igloo/e 32 large 1,053 86 8 1,139 afs600 a3p600 agl600 8.2% 34 proasic plus 32 large 1,228 106 16 1,334 apa450 10.9% 27 axcelerator rtax-s 32 large 579 85 8 664 ax250 rtax250 15.7% 46 table 2 ? coreabc utilization data (soft mode?i nstructions held in ram) (continued) family data width config. comb. seq. ram total device utilization frequency mhz* note: *the frequency given in the table does not apply to the igloo devices. igloo fa mily devices will run significantly slower than the speed listed in the table.
11 1 ? internal architecture coreabc internal architecture is shown in figure 1-1 . the core consists of six main blocks: ? instruction block ? sequencer ?alu and flags ?storage ? analog configuration mux (acm) ? apb controller the instruction block cont ains the instruction counter and the instructi on table that contains the instructions to be executed. in soft mode, these instructions are fetched from ram internal to coreabc. the alu and flags block impl ements the main alu block. each of th e supported operations can be disabled to obtain a minimal-gate-count solution. the storage block provides local st orage for data values and implements the stack required by the call instruction. the acm block implements a small looku p table that can be initialized with the configuration data required by coreai. this allows the analog functions with in a fusion fpga to be easily configured. figure 1-1 ? coreabc block diagram ram register bank and stack storage acm apb data apb interface state machine apb controller apb master interface acm lookup table apb slave interface (nvm mode only) apb access instruction address register next address address +1 address address address operation data data alu alu and flags mult and or xor add shl shr load data z register command sequencer control state machine data out data in address data instruction block instruction register instruction table interrupt parallel i/0 out parallel i/0 in accumulator register
internal architecture 12 the apb controller implements an amba3 apb master interface for controlling both amba3 and amba2 apb peripherals. typically a number of apb peripherals will be in use a nd in such cases the coreapb3 bus interface core should be used to connect the various apb cores to coreabc's master apb interf ace. finally, the sequencer controls the operation of the core , decoding of the instructions a nd enabling of the other blocks. to keep tile counts low, all unused functions within coreabc can be rem oved during synthesis by configuring the core appropriately.
13 2 ? tool flows licenses coreabc is licensed in two ways: ob fuscated and rtl. tool flow functi onality may be limited, depending on your license. obfuscated complete rtl code is provided for the core, enabling the co re to be instantiated, conf igured, and generated within smartdesign. simulation, synthesis, and layout can be performed with acte l libero integrated design environment (ide). the rtl code for the core is obfuscated. rtl complete rtl source code is provided for the core. smartdesign coreabc is available for download to the smartdesign ip catalog via the libero ide web repository. for information on using smartdesign to inst antiate, configure, conne ct, and generate cores, refer to the libero ide online help. the apb master interface of coreabc will typically be connected to the mirrored master interface of coreapb3, with various apb slaves connected to the slave interfaces of coreapb3. the core can be configured using the conf iguration gui within smartdesign. see the "coreabc configuration" section on page 29 for more details on configuring coreabc. simulation flows smartdesign and libero ide facilitate running both a us er (or unit) testbench for coreabc and a basic system testbench for the complete sm artdesign design. you may wish to expand on these simulation capabilities to suit the particular needs of your project. for example, you could make a copy of the system testbench, add additional code to monitor or interact with the design and then use this new testbe nch as stimulus in a simulation. to run the coreabc unit testbench, se t the testbench configuration option to user in the coreabc configuration gui before generating the design. after generation, set the design root to be the coreabc instance and click the simulation (modelsim) button. modelsim will launch and run the unit test. to run the system testbench for the smartdesign design, set the design root to be th e (smartdesign) design after generation and ag ain click the simulation button. modelsim wi ll launch and run th e system simulation. see "testbench and simulation" on page 53 for more details on simulation. synthesis in libero ide to run synthesis with the configurati on selected in the configuration gui, set the design root appropriately and click the synthesis icon in libero ide to launch the synplicity ? synthesis tool. click the run button in the synthesis window to run synthesis.
tool flows 14 place-and-route in libero ide having set the design route appropria tely and run synthesis, click the place&route icon in libero ide to invoke designer. coreabc requires no spec ial place-and-route settings.
15 3 ? coreabc interfaces overview of interfaces coreabc has an amba3 apb master in terface which typically will be c onnected to coreapb3. when in nvm mode (insmode parameter set to 2), an additional amba3 apb slave interface is available for data type access to the (nvm) instruction store. note: when coreabc is mastering coreapb3, the apb slot size configuration option se ttings should match for both of these cores. in soft mode (insmode parameter set to 1), an initialization and configuration (initcfg) interface is available for initializing the ram blocks used as coreabc's instruction store. this in terface is intended to be used to connect to a flash memory system builder (fmsb) ram initialization client. the use of fmsb clients is supported only on fusion devices. on other devi ce families, a different means must be employed to initialize the instruction ram blocks through the initcfg interface. this could involve im plementing some logic to allo w another processor in the system to communicate with the initcfg interface. in addition to the interfaces already me ntioned, coreabc has clock, reset, and interrupt re lated signals as well as general purpose parallel input and out put buses. the widths of these input and output buses are configurable. parameters the parameters described are those directly in the rtl. when working with coreabc in the smartdesign tool, a configuration gui is available for setting these paramete rs. the recommended configur ation flow is to use the configuration gui in smartdesign, which will then set these parameters correctly. importantly, when using the configuration gui, the parameter setti ngs will be cross checked with the coreabc program (which is entered in another tab of the configuration gui) . the configuration gui will indicate any inconsistencies between the program and the parameter settings. see "coreabc configuration" on page 29 for more information on the configuration gui. table 3-1 ? coreabc parameters parameter values description value small medium large apb_awidth 8 to 16 sets the width of the apb address bus. 8 8 8 apb_dwidth 8, 16, or 32 sets the width of th e apb data bus. 8, 16, 32 8, 16, 32 8, 16, 32 apb_sdepth 1 to 16 sets the numbe r of supported apb devices. 1 4 16 icwidth 1 to 16 sets the maximum number of supported instructions. number of allowed instructions is 2 icwidth . icwidth must be ? apb_awidth. 588 zrwidth 0 to 16 sets the width of the z register. a setting of 8 would allow for a maximum value of 2 8 (i.e., 256). zero will disable and remove the z register. 088 iiwidth 1 to 32 sets the width of the io_in input. iiwidth must be ? apb_dwidth. 144 ifwidth 1 to 28 sets how many of the io_in bits can be used with the conditional instruct ions. ifwidth must be ? apb_dwidth ? 4. iowidth 1 to 32 sets the width of the io_out output. iowidth must be ? apb_dwidth. 188
coreabc interfaces 16 stwidth 1 to 8 sets the size of th e internal stack counter used to support the call instruction and interrupt function. the depth of the stack is 2 stwidth . 144 en_ram 0 or 1 when 1, a ram block is used in the core to provide 256 storage locations. this ram is also used to store return addresses for the call and interrupt functions. 011 en_and 0 or 1 when 1, the alu supports the and function. 1 1 1 en_xor 0 or 1 when 1, the alu supports the xor function. 1 1 1 en_or 0 or 1 when 1, the alu supports the or function. 0 1 1 en_add 0 or 1 when 1, the alu supports the add function. 0 1 1 en_inc 0 or 1 when 1, the alu supports the inc function. 0 1 1 en_shl 0 or 1 when 1, the alu supports the shl/rol function. 011 en_shr 0 or 1 when 1, the alu supports the shr/ror function. 011 en_call 0 or 1 when 1, the core supports the call and return operations. 011 en_push 0 or 1 when 1, the core supports the push and pop operations. 011 en_acm 0 or 1 when 1, enables the acm initialization table. 0 1 1 en_datam 0 to 3 controls in ternal multiplexing; see "en_datam parameter" on page 18 . 111 en_int 0 to 2 enables the external interrupt function. when 0, interrupts are disabled. when 1, intreq is active high. when 2, intreq is active low. 011 en_mult 0 to 3 enables the hardware multiplier; four options exist (example for 16-bit core): 0: no hardware multiplier 1: half multiplier, p(15:0) <= a(7:0) * b(7:0) 2: full multiplier returning lower half, p(15:0) <= a(15:0) * b(15:0) 3: full multiplier returning upper half, p(31:16) <= a(15:0) * b(15:0) 000 en_ioread 0 or 1 when 1, the io read instruction is enabled. 0 1 1 en_iowrt 0 or 1 when 1, the iowrt instruction is enabled. 1 1 1 en_aluram 0 or 1 when 1, the bool ean and arithmetic instructions can operate on memory contents. 011 en_indirect 0 or 1 when 1, the z regi ster can be used to generate the apb address, and the apbwrtz and apbreadz instructions are enabled. 001 israddr 0 to 65,535 the address coreabc should jump to when responding to an interrupt request. 0 220 220 table 3-1 ? coreabc parameters (continued) parameter values description value small medium large
parameters 17 insmode 0 to 2 when 0, the instru ctions are contained in internal logic gates, implementi ng a rom function. when 1, internal ram blocks are used to hold the instruction sequence. when 2, internal nvm is used to hold the instruction sequence. insmode = 2 is supported only on fusion devices. 001 act_calibrationdata 0 or 1 when 1, the nvm block containing the calibration data for the device is selected if insmode = 2. when 0, any available nvm block may be used. this option is only applicable when insmode = 2, which implies that a fusion device is being used. n/a n/a n/a imem_apb_access 0 to 2 when 0, apb acce ss to instruction memory is not supported. when 1, read only apb access to instruction memory is possible. when 2, read and write apb access to instruction memory is supported. n/a n/a n/a initwidth 1 to 16 specifies the width of the initaddr input used to initialize the instruction ram blocks when insmode = 1. the actual width depends on several generic values. u tilities used to support soft operation calc ulate this value. 0016 debug 0 or 1 when 1 during simu lation, a detailed log will be generated of the internal operation. n/a n/a n/a testmode 0 to 16 selects a predefined set of instructions used for core verification. this shou ld be set to 0 unless the verification test sequ ences are being used. n/a n/a n/a uniq_string_length 0 to 256 this para meter gives the length (number of characters) of the unique string which is derived from the instance name of a particular coreabc instance. this parameter forms part of the mechanism which allows multiple instances of coreabc to be easily us ed in a single design. n/a n/a n/a max_nvmdwidth 16 or 32 indicates the maximum bit width supported on the data buses connecting to any nvm macro within coreabc. this parameter is only applicable when coreabc is configured to operate in nvm mode which is only possible fo r a fusion device. this parameter is not directly controllable from the configuration gui but is instead automatically set to match the target de vice. a setting of 16 is applied when an afs090 device is targeted. for all other devices the pa rameter is set to 32. n/a n/a n/a table 3-1 ? coreabc parameters (continued) parameter values description value small medium large
coreabc interfaces 18 en_datam parameter this allows various internal multiplexers to be optimized out of the core, lowering tile counts. the settings supported are given in table 3-2 through table 3-5 on page 18 , and the tables show whic h instructions are allowed with each setting. table 3-2 ? accumulator only (en_datam = 0) immediate data accumulator apbwrt no yes + acm ramwrt no yes push no yes loadz no yes iowrt no yes table 3-3 ? immediate only (en_datam = 1) immediate data accumulator apbwrt yes no ramwrt yes no push yes no loadz yes no iowrt yes no table 3-4 ? accumulator and immediate (en_datam = 2) immediate data accumulator apbwrt yes yes + acm ramwrt yes yes loadz yes yes push yes yes iowrt yes yes table 3-5 ? instruction-dependent (en_datam = 3) immediate data accumulator apbwrt no yes + acm ramwrt no yes push no yes loadz yes no iowrt yes no
ports 19 ports all coreabc inputs are sample d, and outputs clocked, on the rising edge of pclk. table 3-6 ? coreabc port descriptions name type description pclk in clock input nsysreset in reset input (a synchronous active low) presetn out reset output; synchr onized version of nsysreset penable_m out apb master interface enable signal pwrite_m out apb master interface write signal psel_m out apb master interface select signal paddr_m[19:0] out apb master interface addr ess bus. the width of this address bus is fixed at 20 bits but some of the upper bits may not be si gnificant, depending on the configurat ion of the core. the number of significant bits is determined by the apb_aw idth and the apb_sdepth parameters. number of significant bits = apb_awidth + log base 2 (apb_sdepth). pwdata_m[x:0] out apb master interface write data bus. the width is controlled by apb_dwidth. prdata_m[x:0] in apb master interface read data bus. the width is cont rolled by apb_dwidth. pready_m in apb master interface ready input. pslverr_m in apb master interface slave error signal. this input cu rrently is not used by coreabc. io_in[x:0] in general-purpose inputs. th e width is controlled by iiwidth. io_out[x:0] out general-purpose outputs. the width is controlled by iowidth. intreq in interrupt request input . when this input is asserted, the instru ction sequence will ju mp to the address set by the israddr parameter. intact out indicates that the core has entered the interrupt service routine. initdataval in enable signal (active high) indicating th at the initaddr and init data inputs are valid. when using a smartgen initia lization client, this si gnal connects to the c lient select signal. initdone in indicates that initializati on has been completed (a ctive high) and the core should start operating. initaddr[x:0] in connects to the initaddr output of the in itcfg block used to configure the ram blocks when insmode = 1. when insmode = 0, these inputs should be tied to logic 0. the width of this input is controlled by the initwidth generic. initdata[8:0] in connects to the initdata output of the in itcfg block, used to conf igure the ram blocks when insmode = 1. when insmode = 0, these inputs should be tied to logic 0. psel_s in select signal of apb slave interface used to access instruction memory in nvm mode penable_s in enable signal of apb slave interface used to access instruction memory in nvm mode pwrite_s in write signal of apb slave interface us ed to access instruction memory in nvm mode. paddr_s[x:0] in address bus of apb slave interface used to access instru ction memory in nvm mode. width is determined by apb_awidth. pwdata_s[x:0] in write data bus of apb slave interface us ed to access instruction me mory in nvm mode. width is determined by apb_dwidth. prdata_s[x:0] out read data bus of apb slave interface us ed to access instruction memory in nvm mode. width is determined by apb_dwidth.
coreabc interfaces 20 pslverr_s out error signal of apb slave interface used to access instruction memory in nvm mode. pready_s out ready signal of apb slave interface used to access instruction memory in nvm mode. table 3-6 ? coreabc port descri ptions (continued) name type description
21 4 ? coreabc programmer?s model coreabc is an accumulator based load/store architect ure with multiple independe nt memory spaces. it is effectively a harvard architecture (inde pendent instruction and data address sp aces). most instructions act only on the accumulator, but there are specific instructions to access the memory spaces described below. address spaces the instruction address space is linear and is implemen ted as a hard-coded instructi on table (hard mode), or an internal instruction ram (soft mode), or an internal nvm block (nvm mode ). this is implicitly accessed by control transfer instructions such as jump and call, but it cannot be directly read or written otherwise, except in the case where apb read/write data type access to inst ruction memory is enabled in nvm mode. in nvm mode, if apb data type read/write access to the instruction memo ry is enabled, it is possi ble to modify or overwrite coreabc's program. normally you will not want to do this and you must take care to ensure that the coreabc program does not unintentionally corrupt itself. in practic e this usually just means setting the sector, page, and spare_page registers in the apb interface to nvm instruction memory to sufficiently high values. that is, read and write data type accesses to the nvm instruction memory should normally be to a region of the nvm above the program which is located from address 0x0000 onwards. see the "apb access to instru ction memory" section on page 51 for more details. the data address spaces are shown in figure 4-1 . there are three separate, independent addressable areas. these are accessed by using instructions or in struction modes unique to each one. internal data ram address space (optional) this is an optional internal 256-loca tion ram storage area. it can be accessed directly using the ramread and ramwrt instructions, and implicitly usin g the push and pop instructions (the st ack, if one is present, is located at the top of ram). the alu instructio ns can also source the secondary ope rand from the ram storage area. the width of each ram location is equal to the data width of the processor (apb_dwidth) or the width of the instruction counter (icwidt h), whichever is greater. i/o address space this is a general-purpose i nput/output area that is accessed by ioread (to load th e accumulator from the input) or iowrt (to write the accumulator to the output) and the in putn test instructions (to read the inputs?for example, jump if input3). figure 4-1 ? coreapb data address spaces i/o ? out ram i/o apb 0xff 0x00 i/o ? in slot n slot 0
coreabc programmer?s model 22 apb address space the apb master interface of coreabc typically will be connected to core apb3 to provide access to up to 16 peripherals. if coreabc is connected to coreapb3, the settings for the apb slot size configuration options of these cores must match. for example, if coreabc is configured fo r a slot size of 256 locations, coreapb3 must also have its slot size set to 256 locations. apb peripherals are accessed by apbwrt (to write to an apb peripheral) and apbread (to read from an apb peripheral). both the slot number and the address within the slot must be specified in these instructions. registers accumulator the accumulator (acc) holds the result of data operati ons and is apb_dwidth (8, 16, or 32) bits wide. z register (optional) the optional z register (z) is a general purpose register which may be used, for exampl e, as a loop counter. the z register is used to provide the address to the apb space when the apbreadz and apbwrtz instructions are executed. when present, the z register is zrwidth (1 to 16) bits wide. flags register?inputs and condition codes coreabc maintains a control register that is used in the conditional instructions ; e.g., jump and call. this register cannot be read or used directly; instead, each name d field can be used to contro l particular instructions. the flags register has two sections, as shown in figure 4-2 . there are three condition code type flags: zero: accumulator zero negative: accumulator negative zzero: register zero there are n inputs ( n ? 28), input0 ? input n , which are directly mapped to the general purpose inputs connected to coreabc's io_in[n:0] port. the number of these is configurable up to the lower of 28 or apb_dwidth ? 4, where apb_dwidth is the widt h specified for the external apb data bus. from these basic fields, other condi tions are constructed and made av ailable in the instruction set. instruction set table 4-1 through table 4-8 on page 26 list the supported instructions. on the right hand side of these tables there are columns entitled flags and cycles. the flags column c ontains two sub-columns, acc. zero and acc. neg., and the entries under these columns are either yes or no. "yes" indicates that the relevant flag, accumulator zero (acc. zero) or accumulator negative (acc. neg.), is affected by the instruction named in that row of the table. similarly, a figure 4-2 ? flags and inputs register inputn input0 z register zero acc neg acc zero
instruction set 23 "no" entry indicates that the flag is not affected by the instruction. the entries in the cycles column give the number of (pclk) clock cycles required for each instruction. table 4-1 ? the boolean and arithmetic instruction group instruction 1, 2 description flags cycles acc. zero acc. neg. load dat data load accumulator with value. yes yes 3 load ram address load accumulator with value. yes yes 3 and dat data bitwise and accumulator with immediate data. yes yes 3 and ram address bitwise and accumulator wi th ram location. yes yes 3 or dat data bitwise or accumulator with immediate data. yes yes 3 or ram address bitwise or accumulator with ram location. yes yes 3 xor dat data bitwise xor accumulator with immediate data. yes yes 3 xor ram address bitwise xor accumulator with ram location. yes yes 3 inc increment accumulator. yes yes 3 dec decrement accumulator. yes yes 3 add dat data add immediate data to accumulator. yes yes 3 add ram address add ram location to accumulator. yes yes 3 sub dat data subtract immediate data from accumulator. sub ram is not supported. yes yes 3 mult dat data multiply accumulator by immediate data. core parameters determine multiplier return value. yes yes 3 mult ram address multiply accumulator by ram location. core parameters determine multiplier return value. yes yes 3 cmp dat data compare accumulator to immediate data. zero set if equal; negative set if msbs differ. yes yes 3 cmp ram address compare accumulator to ram location. zero set if equal; negative set if msbs differ. yes yes 3 cmpleq dat data compare accumulator to immediate data. zero set if equal; negative set if acc < data. cmpleq ram is not supported. yes yes 3 shl0 shift accumulator left and infill with 0. yes yes 3 shr0 shift accumulator right and infill with 0. yes yes 3 shl1 shift accumulator left and infill with 1. yes yes 3 shr1 shift accumulator right and infill with 1. yes yes 3 shle shift accumulator left and infill with lsb. yes yes 3 shre shift accumulator right and infill with msb. yes yes 3 notes: 1. for most instructions, when using the con figuration gui, the dat ke yword can be omitted. 2. dat may be replaced with dat8 or dat16 when only lower 8 or 16 data bits contain valid data. using dat8/dat16 will reduce tile counts when instruct ions are held in logic tiles (t hat is, when the core is configured to operate in hard mode).
coreabc programmer?s model 24 rol rotate accumulator left. yes yes 3 ror rotate accumulator right. yes yes 3 bitclr data clear one bit in accumulator specified by argument (and). in this case, the data value specifies the bit position. yes yes 3 bitset data set one bit in accumulator specified by argument (or). in this case, the data value specifies the bit position. yes yes 3 bittst data test one bit in accumul ator. zero set if all requested bits are clear. in this case, the data value specifies the bit position. yes yes 3 table 4-2 ? the memory instruction group instruction description flags cycles acc. zero acc. neg. push push the accumulator onto the stack. no no 3 push acc push the accumulator onto the stack. no no 3 push dat data push immediate data onto stack. no no 3 pop pop data from the stack to the accumulator and update the flags. yes yes 3 ramwrt address acc write accumulator to ram address. yes yes 3 ramwrt address dat data write immediate data to ram address. yes yes 3 ramread address read data from ram address to the accumulator and update the flags. no no 3 table 4-1 ? the boolean and arithmetic instruction group (continued) instruction 1, 2 description flags cycles acc. zero acc. neg. notes: 1. for most instructions, when using the con figuration gui, the dat ke yword can be omitted. 2. dat may be replaced with dat8 or dat16 when only lower 8 or 16 data bits contain valid data. using dat8/dat16 will reduce tile counts when instruct ions are held in logic tiles (t hat is, when the core is configured to operate in hard mode).
instruction set 25 table 4-3 ? the z register* instruction group instruction description flags cycles acc. zero acc. neg. loadz acc load z with accumulator. no no 3 loadz dat data load z with immediate value. no no 3 addz acc add accumulator to z and store in z. only zzero flag is affected. no no 3 addz dat data add immediate data to z and store in z. only zzero flag is affected. no no 3 subz dat data subtract immediate data from z and store in z. only zzero flag is affected subz acc is not supported. no no 3 incz increment z. only zzero flag is affected. no no 3 decz decrement z. only zzero flag is affected. no no 3 note: *the z register is intended to be used as loop counter or apb address register. table 4-4 ? the apb instruction group instruction description flags cycles acc. zero acc. neg. apbread slot address read from apb. no no 5 apbwrt acc slot address write accumulator to apb at chosen address. no no 5 apbwrt acm slot address write value of acm table, at location given by accumulator, to apb at chosen address. no no 5 apbwrt dat slot address data write data to chosen address. no no 5 apbreadz slot read from apb. the z register specifies the apb address. no no 5 apbwrtz acc slot write accumulator to apb. the z register specifies the apb address. no no 5 apbwrtz acm slot write value of acm table, at location given by accumulator. the z register specifies the apb address. no no 5 apbwrtz dat slot data write data; the z register specifies the apb address. no no 5 table 4-5 ? the i/o instruction group instruction description flags cycles acc. zero acc. neg. iowrt acc write accumulator to i/o register. no no 3 iowrt dat data write data value to i/o register. no no 3 ioread load the accumulator with the i/o input value. no no 3
coreabc programmer?s model 26 table 4-6 ? the flow control instruction group instruction description flags cycles acc. zero acc. neg. jump condition $label jump to label. no no 3 jump if/ifnot condition $label jump on condition to label. no no 3 wait until/while condition stop at this instruction until condition is true. no no 3 call $label as jump, but puts return address on stack. no no 3 call if/ifnot condition $label as jump, but puts return address on stack. no no 3 return return from a call. no no 3 return if/ifnot condition return from a call on condition. no no 3 retisr condition return from an interrupt. no no 3 retisr if/ifnot condition return from an interrupt on condition. no no 3 halt stop at this instruction. interrupts will still be processed. halt is a synonym for wait, and generally used without a condition. no no indefinite table 4-7 ? conditions for flow control instruction group condition description always always. you can get th e same effect as this by not specifying any condition. zero accumulator zero negative accumulator negative zzero z register zero input0 input0 set input1 input1 set and similarly for higher inputs, if available. positive equivalent to not negative lte_zero less than or equal to zero; the combination negative or zero gt_zero greater than zero; the combination not (negative or zero) table 4-8 ? other instructions instruction description flags cycles acc. zero acc. neg. nop no operation no no 3
27 5 ? coreabc operation acm lookup table for use with coreai when generating a smartdesign design that contains an inst ance of coreabc, a check is made to detect if an instance of coreai is bei ng mastered by coreabc?s apb master interfa ce. coreai may be connected directly to coreabc if it is the only apb slave be ing controlled by coreabc but, more typically, coreai will be one of a number of slaves under the control of coreabc, with al l the cores connected together using the coreapb3 bus fabric core. in either scenario the presence of co reai in coreabc?s apb address space will be detected. if coreabc is controlling a coreai in stance, a lookup table will be implemen ted within coreabc. this lookup table will hold data for initializing th e coreai analog configuration multiplexer (acm) and the table?s contents will be derived from the configuration information entere d in coreai?s configuration gui. the apbwrt acm instruction can be used in coreabc?s program to easily load the acm initialization values for coreai. this instruction uses the accu mulator value to index into the acm lookup tabl e to generate the actual data value written. the "example instructi on sequence" on page 69 shows the initialization of acm registers (within the instruction loop beginning with the label "$waitregprog"). note: coreai is a fusion-specific core, which means that it can only be used on a fusion device. this implies that the acm lookup table and the apbwrt acm instructio ns described in the preceding paragraphs are only relevant when designing for a fusion device. stack the upper 2 stwidth memory locations in the 256-location internal storage are used for stor ing the stack contents. if stwidth = 4 (stack is 16 locations de ep), the stack will occupy locations 0xf0 to 0xff. there is no underflow or overflow detection on the stack poin ter, so it will simply wrap around from 0xf0 to 0xff on push operations and 0xff to 0xf0 on pop operations (assuming stwidth = 4). the ramread and ramwrt instructions can be used to read and modify the values pushed onto the stack. an indirect jump instruction ca n be implemented by pushing the required jump address on the stack and executing a return instruction. interrupt operation when intreq is asserted, the core will jump to the interrupt service routine (isr) on completion of the current instruction. as it does so, it will assert the intact (inter rupt active) output. the last instruction in the isr should be a retisr (return from isr) instruction. when the retisr instruction is exec uted, the intact output is cleared. intact acts as the interr upt acknowledge, and intr eq should be deactivate d when intact becomes active. the core will ignor e additional interr upt requests while intact is active. the core will respond to an interrupt re quest within six clock cycles?five cloc k cycles for the current instruction to complete, 1 plus one additional cl ock cycle in the core. the value held in the instruction c ounter is pushed onto the stack on enteri ng the interrupt service routine. this value is popped from the stack when exiting the routine to provide the return address. the contents of the zero and negative flags are saved internally (rather than on the stack) on entry to the interrupt service routine and restored on the retisr instruction. when the isr is en tered, the zero and negative flags will contain the flag values present when the previous isr was executed. the accu mulator register is not saved on entry to the isr. the isr should push and pop the accumula tor to preserve its contents. the intreq polarity can be acti ve low or active high. this is set by the en_int parameter. 1. if an apb-related instruction (such as apbread or apbwrt) is active when the in terrupt occurs, more than five cycles may be required for the instruction to complete if the apb access is extended by pulling the pready_m input low for a number of cycles .
coreabc operation 28 if an interrupt occurs when the halt or wait instructio ns are being executed, then, after completion, the isr will return to the halt or wait instruction, unless the is r does something to remove the reason for the wait or modifies the stack contents; e.g., it could pop the return address, modify it, and push it back on the stack. when the interrupt functionality is being used, coreabc' s program will often be struct ured such that the first instruction (at instruction address 0) is a jump to the main loop of the program and the isr will be located immediately after this, at instruction addr ess 1. the instructions of the main l oop will be located just after the isr in the program memory.
29 6 ? coreabc configuration the coreabc configuration gui is launched when instantiating the core in a smartdesign design. after instantiation, the confi guration gui can be opened by double-clicki ng on the coreabc instance or by right- clicking and selecting configure component . the configuration gui has three tabs : parameters, progr am, and analysis. select the parameters tab on the core abc configuration gui to begin configuring the core. when you do this, you will see the screen shown in figure 6-1 . figure 6-1 ? configuration parameters
coreabc configuration 30 configurable options each of the configurable options presented on the parameters tab of the configuration gui is explained in the following sections. data bus width selects the width of the data bus within coreabc and on the apb master interface (and on the apb slave interface, if present). possible settings are 8, 16, or 32 bits. the accumulator width is equal to the value set for data bus width. number of apb slots this sets the maximum number of apb slots coreabc can address. each slot is a lo cation for connecting an apb peripheral, so ensure that you allocate enough slots for your design. it is easy to set this at a later stage in your design if you wish, when you have a clear understanding of the peripherals you are connecting. apb slot size this sets the number of locations in each apb slot. possible settings range from 256 to 64k locations. this setting should match the corresponding setting (also called apb sl ot size) on any instance of coreapb3 mastered by coreabc. maximum number of instructions this allocates the instruction space for your program (in a range from 2 to 65,536 instructions). you should not make this larger than necessary, as it is used for config uring multiplexers and will directly impact the size of the core. z register size this sets the maximum z register size you intend to use in your program. this is used to set the size on the z register and associated logic, so the smaller you make it, the smaller your core. ther e is also a disable setting to remove this feature. number of i/o inputs this sets the number of inputs confi gured on coreabc. these can be read using the ioread instruction. the range is 1?32. number of i/o flag inputs this sets the number of inputs connected into the conditional logic. these are accessible for cont rolling jump and similar instructions as input0 ? input27 (note that the first i nput is input0!). the range is 1?28. number of i/o outputs this sets the maximum number of outpu t lines from coreabc. the range is 1?32. these can be written to using the iowrt instruction, which allows the accumulator to be written to the output register. stack size call and return instructions use a st ack to store the return address when subroutines are used. the stack size can be set in this drop-down list. note that this list will be grayed out (d isabled) if internal data/stack memory is not enabled, because the stack is allocated from that memory.
configurable options 31 instruction store this is a very important setting that determines whether coreabc is in hard, soft, or nvm mode. the options are as follows: hard (fpga tiles) ? the program instructions are stored in fpga tiles which are effectively used to build a hard-coded rom. no ram or nvm blocks are instantiated for instruction storage. soft (fpga ram) ? the program instructions are stor ed in ram blocks instantiated inside coreabc. nvm ? the program instructions are stored in an nvm block instantiated within coreabc. this instruction store option is only availa ble on fusion devices. init/config address width this is only applicable when instruction store is set to soft. this option sets the address width of the initcfg interface for initializing the ram blocks which provide th e instruction store inside a soft mode coreabc. the easiest way to determine the setting for this option is to look at the instruction store details section under the analysis tab. the fifth bullet point in this section gives the requ ired width in number of bits. instruction store apb access this is only applicable when instruction store is set to nvm. this option sets the type of access to the instruction store nvm. possible settings are none, read only, or read/write. use calibration nvm this check box option is only applicable when instruct ion store is set to nvm a nd, when selected, causes coreabc to request use of the nvm bloc k holding the device calibration data fo r its instruction store. one of the nvm blocks on the device will hold the calibration data in a spare pa ge. checking this option causes the act_calibrationdata parameter to be set to 1 on the nvm instance within (an nvm mode) coreabc instance. it is possible that some ot her nvm instance not related to core abc in the design may also have its act_calibrationdata parameter set to 1. in this case , coreabc is not guarantee d to be allocated the nvm block holding the calibration data. internal data/stack memory set this option on if you are going to use the internal scratchpad ram (with ramread and ramwrt instructions) or the stack (for call and return instructions). alu operation from memory this allows the alu data input to accept both immediate data and data from the ram. it enables add ram and similar instructions. apb indirect addressing this allows the z register to be used as the source of the apb address for apb instructions (that is, setting this option effectively enables instructi ons such as apbreadz and apbwrtz). supported data sources this controls the en_dat am parameter; refer to "en_datam parameter" on page 18 . setting this to ?accumulator and immediate? will increase tile counts. interrupt support this allows you to enable or disable interrupt suppo rt. if you specify active high or active low interrupt, the interrupt logic is automatically included. when you enable the interrupt logic, you should also set the isr address .
coreabc configuration 32 isr address the isr address should be set when you have enabled the interrupt logic. it is the instruction address from which coreabc will fetch the ne xt instruction to be executed after an interr upt is detected. at the end of the isr, you will have a return from interrupt (r etisr) instruction. th e default value for isr address is 1. this setting is suitable for a program which is structured such that the first instructi on (at address 0) is a jump to the main part of the program and the isr is located from address 1 onw ard (the main part of the program would be located just after the isr code). optional instructions there is a range of instructions that can be omitted or included in corea bc to control the size. this empowers you to make size/performance tradeoffs. if you have used omitted instructions in your program, you will receive a validation warning. license this option is used to generate eith er obfuscated or plain text rtl code for the core, depending on the type of license you have. an obfuscated license enables you to generate obfuscated rtl code . an rtl license permits generation of either obfuscated or plai n text rtl code. testbench set this to user if you want a user testbench generate d with your core. verbose simulation log this enables the feature that allows coreabc to log the operations being performe d during simulation along with the current accumulator values. see the "testbench and simulation" section on page 53 for more details. cross-validation of configuration fields there is extensive cross-validation of settings in the coreabc configuration screen to ensure that the overall configuration is consistent. this al so extends to validation between the program and the configuration. most possible inconsistencies are covered. figure 6-3 shows the symbols that are di splayed to indicate a possible error. when you click the symbol ( figure 6-2 ), information is given as to th e precise nature of the problem. figure 6-2 ? error symbol
cross-validation of configuration fields 33 in the example shown in figure 6-3 , the maximum z register has been set to disabled, but there is an instruction in the program (loadz) which re quires that the z register features are available. in general, the validation is more ex tensive on the parameters tab than on th e program tab, so it is a good idea to take a look at the parameters tab when you have completed writing your program. some cross-validation actually grays out fields that are inappropriate when other settings have not been made. figure 6-3 ? coreabc configuration validation
nvm data width on afs090 device on an afs090 device, the data width when accessing nvm is li mited to a maximum of 16 bits. on other fusion devices, 32 bit access to nvm is supported. this has implications wh en targeting an nvm mode coreabc design at an afs090 device. for such a design, if a data bus width of 32 is selected along with read only or read/write apb access to the instruction store nvm, the following message will be displayed on pressing the ok button of the coreabc configuration gui: as the message indicates, apb accesses to the nvm instruction store will be limited to 16 bits in this case even though a data width of 32 has been sele cted. 32 bit access is supported to any other slaves which may be connected to the apb bus. click the ok button on this message to dismiss the message (and the coreabc configuration window). figure 6-4 ? afs090 data width message
35 7 ? coreabc programming coreabc programs are written and assembled under the program tab of the coreabc configuration gui, as shown in figure 7-1 . you can view an analysis of your code under the analysis tab. figure 7-1 ? coreabc programming screen
coreabc programming 36 analysis if the analyze program as i type check box is selected (under the program tab), your program is continuously analyzed as you write it, to detect any syntax or other errors. these errors ar e immediately flagge d, and information about them is provided. colo r coding of the program is used, with commen ts appearing in green, valid instructions in blue, and errors in red. as the pr ogram becomes larger, analysis takes l onger with each char acter typed and this eventually impacts usability. if this is an issue, you can turn off analysis (by clearing the check box) when you enter the program. you can then turn on the analysis again when the program is complete or almost complete. under the analysis tab, you will find us eful information and statistics on your program, most of which is self explanatory. for example, the instructions used in the pr ogram are listed and this information may be useful for optimizing your coreabc instance by omitting support for any unused instructions (under the optional instructions section of the parameters tab). in soft or nvm mode, the analys is tab will also co ntain information of use when creating a flash memory system buil der data storage or initialization client. coreabc instruction modes the instruction store configuration opt ion (insmode parameter) controls how coreabc?s instructions are stored. for all device families, hard mode and soft mode instruction stores ar e possible. for the fusion family, an additional nvm mode is al so available. each of these instruct ion storage modes is described below. hard mode in hard mode, the instructions are stored in fpga tiles. essentially, tiles are used to build an instruction rom. the instructions.v or instructi ons.vhd rtl file implements the instruction store and this file is automatically created when a coreabc based design is generated within smartdesign. from a design implementation point of view, hard mode is probably th e simplest mode. the rtl files completely describe the core and its program and can simply be run through synthesis, compile, layout, et c., along with any other components in the design. soft mode in soft mode, the instructions are stored in ram blocks on the device. the number of ram blocks required to hold the program increases with increasing program size and instruction width. the inst ruction width increases with increasing address width (apb_awd ith), data width (apb_dwidth), an d number of locations per apb slot (apb_sdepth). details on the instruct ion width and the number of instruct ion store ram blocks required can be found under the analysis tab of the coreabc configuration gui. in soft mode, the instructram.v or instructram.vhd rtl f ile instantiates th e required number of ram blocks within coreabc. when a design containing a soft mode coreabc instance is generated in smartdesign, memory files are created for initializing the instruct ion ram blocks during simulation. th ese files (one per ram block) are automatically placed in the project?s simulation folder to facilitate easy simulation. in addition to these files, a single, consolidated memory file is created. this file is intended for use in initializing the instruction ram when the design is implemented on a device. wh en a fusion device is being used, this consolidated memory file typically will be used to create a ram initialization client usi ng the flash memory system bu ilder (fmsb) utility. for a non-fusion device, you must manual ly implement some other means of initializing the ram blocks.
coreabc instru ction modes 37 soft mode flow on a fusion device the following sequence of steps descri bes how to implement a soft mode coreabc instance on a fusion device. the steps describe the use of an fmsb ram initiali zation client to initialize coreabc?s instruction ram. 1. set the instruction store option to soft (fpga ram) as shown in figure 7-2 . if there are any validation warnings, ensure that the init/config address width is configured appropriately. figure 7-2 ? init/config address width
coreabc programming 38 2. in the coreabc configurator analysis view, as shown in figure 7-3 , note the configuration details which will be needed when configuring a fusion flash memory system builder [ram] initialization client. 3. these fmsb initialization client configuration details are also written to the coreabc.log file, which appears in the design explorer > files view under components > [smartdesign-name] > report files. figure 7-3 ? initialization client configuration
coreabc instru ction modes 39 4. save the coreabc configuration. note in smartdesign that the initcfg bus interface now appears on the coreabc instance ( figure 7-4 ). 5. the next task is to instantiate, configure, stitc h, and generate a fusion fl ash memory system builder initialization client into the design to store the soft mode program image in an nvm block and to initialize the coreabc soft mode program storage ram blocks at startup time. however, we do not yet have the required soft mode program image so cannot do this yet. for this reason we must generate the currently incomplete design first. choose smartdesign > generate design. you will get a warning about the coreabc initcfg bu s interface not being conne cted, but you can ignore this for now (or temporarily mark this bus interface unused wh en generating here) . 6. open the coreabc.log file mentioned in step 2 so th at you can view the configur ation details required for the soft mode coreabc?s fmsb init ialization client. select and copy the name of the actel-binary format ram memory image file and keep co reabc.log visible while configuring the fmsb initialization client. figure 7-4 ? coreabc instance
coreabc programming 40 7. go to the libero ide catalog, expand the tree view under fusion peripher als and double-click on the flash memory system builder . choose an initiali zation client, click add to system, and then configure the client to match the detail s given in coreabc.log ( figure 7-5 ). figure 7-5 ? modify initialization client
coreabc instru ction modes 41 8. click ok and then generate. name the instance and click ok again. back in smartdesign, the flash memory system builder initialization client instance should now appear as shown in figure 7-6 . figure 7-6 ? flash memory system builder initialization client
coreabc programming 42 9. select the initialization client instance and choose smartdesign > auto connect selected instance(s) and smartdesign will connect the coreabc?s slave in itcfg slave interface to the initialization client?s master interface. manually connect the remaining initialization client?s signals, as shown in figure 7-7 . 10. the design is now complete and can be generated using smartdesign > ge nerate design. 11. go to the libero ide proj ect flow view and click on synplify ? to run synthesis. 12. when synthesis has completed, exit synplify and then click on place & route to run compile, layout, and programming file generation. figure 7-7 ? connect initialization client?s signal
coreabc instru ction modes 43 13. when you click on programming file in designer to run fl ashpoint, to ge nerate the programming file (a pdb file, for example), you will get the warning shown in figure 7-8 if the smartdesign design was recently regenerated. this is because the fmsb in itialization client?s input ac tel binary soft mode program image file is more recent than the generated efc file, so you need to re import the update d input file . 14. click on modify > import content and reimport the soft mode actel binary memory image file. the import dialog should open on the correct folder containing the file (i.e., \component\work\\). click ok and then finish to generate the programming file (pdb file). click generate and, if warned about overwriting a previously generated programming file , accept/confirm this. once the progr amming file button in designer turns green, exit designer and return to the libero ide program flow view. 15. you can now program the device. the program image will be programmed into an nvm block and, at startup time, this image will be used to initialize the soft mode coreabc instruction ram blocks. 16. important: if you change your coreabc configur ation or program, you must ensure that the initialization client confi guration matches the details presented in the coreabc configurator?s analysis view. if you forget to do this, it could result in an in correctly formatted or incomplete program image being stored or initialized to coreabc ram blocks. nvm mode with a fusion device it is possible to set the instruct ion store option to nvm. when th is setting is selected, the coreabc program is stored in an nv m block and the instructions are re ad directly from nvm during operation. in nvm mode, the instructnvm .v or instructnvm.vhd rtl file instantiat es an nvm block within coreabc. when a design containing an nvm mode corea bc instance is generated in smartdes ign, memory files are created for initializing the nvm block during simu lation and to enable the nvm block to be programmed with the program image during programming of the fusion device. the simulatio n-related memory file is automatically placed in the project?s simulation folder to facilitate easy simulation. the file which is related to programming of the nvm block has a *.hex suffix and contains information in the intel hex format. this file is intended to be used to create a data storage client using the flash memo ry system builder (fmsb) utility. figure 7-8 ? import updated input file
coreabc programming 44 nvm mode flow on a fusion device the following sequence of steps describes how to im plement an nvm mode coreabc instance on a fusion device. the steps describe the creation of an fmsb data storage client to produce an embedded flash configuration (efc) file which contributes to the overall programming file for the device . the coreabc program is effectively contained in this efc file. 1. set the instruction store option to nvm, as shown in figure 7-9 . figure 7-9 ? instruction store option
coreabc instru ction modes 45 2. the coreabc configurator analysis view note ( figure 7-10 ) shows the configurati on details which will be needed when configuring a fusion flash memo ry system builder da ta storage client. the coreabc generator also emits a text version of the analysis view content into a log file ( \component\work\ \\coreabc.log). it will appear in the design explorer > files view under components > [s martdesign-name] > report files > coreabc.log. this will be used in the following step s when configuring the fmsb data storage client. 3. choose smartdesign > generate design. 4. go to design explorer > files > components > [smartde sign-name] > report files and open coreabc.log, which contains the same details as the coreabc configurator analysis view. in particular it includes the details required for configuration of the fusion flash me mory system builder data storage client required for the nvm mode coreabc instan ce. scroll down to the fusion flash memory system builder data storage client configuration section. select and copy the name of the nvm mode intel-hex figure 7-10 ? analysis view
coreabc programming 46 memory image file. you will paste this into the fmsb data storage client configuration in a subsequent step. keep the coreabc.log file ope n so that it is visible and you ca n see the other fmsb data storage client configuration deta ils during the next steps. 5. in the libero ide ca talog, right-click the fusion peripherals > flash system memory builder core and choose configure core ( figure 7-11 ). it is not necessary to create an fmsb instance (by double-clicking or choosing instantiate in ), although creati ng one will not ca use a problem. 6. select data storage client type and click add to system, as shown in figure 7-12 . figure 7-11 ? configure core figure 7-12 ? add data storage
coreabc instru ction modes 47 7. configure the data storage client according to the details displayed in the coreabc.log file. in particular, paste the nvm memory image file name copied earlier into the memory content file field and enter a client name. configure the start address , size of word, and number of words options ( figure 7-13 ). figure 7-13 ? configure data storage client
coreabc programming 48 click ok and then generate. name the core when prompted. th e configured fusion flash memory system builder data stor age client component should now appear under the hierarchy tab in your design explorer, as shown in figure 7-14 . 8. go to the libero ide pr oject flow vi ew and click synplify to run synthesis. figure 7-14 ? hierarchy tab in design explorer
coreabc instru ction modes 49 9. when synthesis has completed, exit synplify and then click place & route to run compile , layout, and programming file genera tion. when you click programming file in designer to run flashpoint to generate the programming file (pdb file ), you will receive the warning shown in figure 7-15 . figure 7-15 ? block not configured warning
coreabc programming 50 in this case it is necessary to update the configuration. click modify to get the dialog shown in figure 7-16 . click import configuration file . browse to and select the relevant efc file for the coreabc nvm mode program image. the efc file should be in a subfolder of the \smartgen folder. in this example, the file has the following location: \smartge n\abc_program_in_nvm\ abc_program_in_nvm.efc. if the smartdesign design was regene rated more recently than the fsmb data storage client (which is quite likely), y ou will receive the warning shown in figure 7-17 because the input in tel hex file is more recent than the generated efc file. click import content to import the nvm mode program image intel hex file (the import dialog should open on the correct folder containing this file). figure 7-16 ? modify block dialog figure 7-17 ? client content file has changed warning
coreabc instru ction modes 51 once you have done this, the configuratio n should be up to date, as shown in figure 7-18 . click ok, finish, and then generate . you may be asked to confirm the overwriting of a previously generated programming (pdb) file, in which case confirm/accept this. 10. once the programming file has been generated, exit designer and return to the libero ide program flow view. you can now program the board with your coreabc nvm mode design. 11. important: bear in mind that if you change the core abc program such that it becomes longer than the size (number of words) previously configured in the fusion flash memory system builder data storage client component (see step 7 ), you will need to reconfigure and re generate the file. for this reason you should always double check the coreabc analysis view nvm program details against the currently configured fmsb data storage client configuration to en sure consistency. apb access to instruction memory in nvm mode, it is possible to access the internal nvm block that stores coreabc?s instructions through the apb slave interface. this functionality allows coreabc to l og and retrieve information to and from nvm, for example, while simultaneously running from nvm in cases where onl y one nvm block is available for use by the coreabc subsystem. the instruct ion store apb access configuration option is used to select the type of apb access (if any) to the instruction memory in nvm mode. possible options are: none, read only, or read/write. note: where read only or read/write access to the instruction memory is required, the apb slave interface which provides access to the instruction memory should only be mastered by coreabc?s apb master interface, typically via coreapb3. a separate, independent ap b master should not be used to communicate with coreabc?s slave apb interface because this is likely to lead to erro neous behavior. arbitration between instruction fetches and data type read /write from/to (nvm) instruction memo ry is deliberately kept as simple as possible to minimize the size of coreabc. the apb slave interface provides a register interface for accessing the nvm bl ock. page, sector, and spare_page registers together are used to select a 128-byte page to be held in the nvm?s page buffer. the page in the buffer can be read an d written directly at offset 0x00 to 0x7f in the apb slave interface address space. if writes have been used to m odify the contents of the page buffer and th e new data is required to be saved in the nonvolatile array of the nvm, the pr ogram_enable and program registers must be wr itten (in that order, using any data) to cause the new page to be programmed to the array. the process of programming the array takes around 8 milliseconds to complete, duri ng which time core abc will stall. it is possible for a coreabc program to overwrite or corrupt itself when ap b read/write access to the instruction memory is enabled in nvm mode. you must take care to a void this. in practice this usually just means setting the sector, page, and spare_page registers in the apb interface to nvm instruction memory to sufficiently high values. that is, read and write da ta type accesses to the nvm instruct ion memory should normally be to a region of the nvm above the program whic h is located from address 0x0000 onwards. figure 7-18 ? configuration up to date
coreabc programming 52 table 7-1 describes the register inte rface used to access the in ternal nvm block using the apb slave interface . table 7-1 ? address map of apb slave in terface, nvm mode only offset register name r/w width reset value description 0x00 to 0x7f (this is a range of offsets; see description column for more information.) r/w apb_dwidth (8, 16, or 32) ? any access within this ra nge of offsets accesses offset[6:0] in the page held in the nvm page buffer addressed by {spare_page_reg + sector_reg + page_reg}. if apb_dwidth = 8, consecut ive bytes are at offsets 0x00, 0x01, 0x02, etc. if apb_dwidth = 16, consecutive halfwords are at offsets 0x00, 0x02, 0x04, etc. if apb_dwidth = 32, consecutive words are at offsets 0x00, 0x04, 0x08, etc. the address to the nvm is always a byte address and the lower one or two bits of the address are ignored when the data size is 16 or 32 bits. this means that misaligned addresses are automatically aligned. on an afs090 device, the data width is restricted to 16 bits when accessing nvm. when apb_dwidth is set to 32 in a design targ eted at an afs090 device, apb accesses to the nvm instruction memory will be consistent with the beha vior for apb_dwidth = 16. that is, only the lowest bit of the (byte) address to the nvm is ignored and only the lower 16 bits of the read and write data buses carry valid data. 0x80 page_reg w 5 0x0 page of nvm being accessed during apb accesses (to an offset in the range 0x00 to 0x7f). bits [11:7] of address input to nvm block. 0x84 sector_reg w 6 0x0 sector of nvm being accessed dur ing apb accesses (to an offset in the range 0x00 to 0x7f). bits [17:12] of address input to nvm block. 0x88 spare_page_reg w 1 0x0 drives spar epage input to nvm during apb accesses (to an offset in the range 0x00 to 0x7f). 0x8c reserved 0x90 reserved 0x94 program_reg w 1 0x0 any write to this register (regardless of the value written) will cause the contents of the page buffer to be programmed to the nvm array, provided the program_enable bit is set (see program_enable_reg at offset 0x9c). 0x98 reserved 0x9c program_enable_reg w 1 0x0 any write to th is register (regardless of the value written) causes a program_enable control bit to be set. this register is cleared by any access (read or write) to any other apb address. this means that the register will be cleared by writing to the program_reg. this register is also cleared if it is read.
53 8 ? testbench and simulation unit testbench a unit (or user) testbench is packaged with corea bc. a block diagram of th e testbench is shown in figure 8-1 . identical testbenches are suppl ied for both the vhdl and ver ilog versions of the core. the coreabc unit testbench runs a canned program to exercise the core. apb slave models which effectively implement some memory are included in the testbench to allow verification of write a nd read back operations on the apb interface. to run the unit testbench, simply set the design root to the coreabc instance (using right-click, set as root on the instance name in the hierarchy tab of the design explorer) and click on the simulation (modelsim ? ) button in the project flow. the unit testbench should automatically launch and run. a "tes ts complete ... okay" type message will appear in the simulator transcript window if the simula tion is successful. system simulation to simulate a coreabc based design created in smartdesig n, generate the design and then ensure that the design root is set to the smartdes ign design. during generation of the design, a basic system testbe nch is created which instantiates the design and pr ovides clock and rese t signals to the design. clicking on the simulation (modelsim) button will run this test bench. when running the system testbench, coreabc will execute the program entered in the program tab of its configuration gu i, rather than a canned program, as is the case when running the coreabc unit testbench. by default, the system test bench will run and the clock and reset signals wi ll be displayed in modelsim's waveform viewer. often you will want to browse into the design an d select other signals to di splay in the waveform viewer before restarting and re running the simulation from within the simulator. figure 8-1 ? coreabc verification testbench apb bus apb slave model apb slave model core abc
testbench and simulation 54 simulation logging coreabc includes debug code that logs the operations being performed dur ing simulation, along with the current accumulator values. a typical log is shown below. # ins:141: xor 00 <= 0a xor 0a flags:zero # ins:142: jump (not taken) not zero # ins:143: nop # ins:144: load 00 <= 00 flags:zero # ins:145: loadz <= 5h this log starts at instruction 141 and shows the accumulator being xored with 0x0a, a jump testing the zero flag, a nop instruction, and the accumulator being loaded with 00. finally, the internal z register is loaded. this feature is only available when pre-synthesis simulation is carried out . during synthesis, the debug code is removed from the core. to enable this feature, select the verbose simulation log option on the coreabc configuration gui.
55 9 ? example design using coreabc this section describes the creation of a simple coreabc based design. the design uses the general purpose outputs of coreabc to control eight outputs wh ich may, for example, be used to drive leds on a pcb. a "rotating 1"pattern is produced on the outputs an d coretimer is used to create a de lay between pattern changes. coreapb3 provides the bus fabric that connects the processor and timer peripheral together. the design is illustrated in figure 9-1 . in this example, a hard mode coreabc will be used and the design will be ta rgeted at a fusion device. follow the instructi ons beginning in the "create a new project" section on page 56 to create the example design. figure 9-1 ? example coreabc design coreabc coretimer 16 16 outputs coreapb 3 io_in io_out intreq timint outputs are looped back to inputs
example design using coreabc 56 create a new project the first task is to create a new project using the libero ide project manager. use the fo llowing steps to create the project: 1. start project manager and select project > new project . the new project wizard will appear. enter coreabc_example as the project name and select verilog as the preferred hdl type, as shown in figure 9-2 . figure 9-2 ? new project wizard
create a new project 57 2. click next and on the next screen choose fusion for the family and select the afs600 die and the 484 fbga package, as shown in figure 9-3 . 3. click finish to exit the new project wizard. figure 9-3 ? select family, die, and package
example design using coreabc 58 create a smartdesign design click on the smartdesign button in the project flow window and enter abc_system as the name of the smartdesign component to be created, as shown in figure 9-4 . click the ok button and the smartdesign canva s for the abc_system will open. instantiate, configure, and connect the components components can be instantiated on th e smartdesign canvas by dragging and dr opping from the catalog pane on the right hand side of the project manager. when a component is dropped onto the canvas, a configuration window will open for that instance of the component. you may need to expand some of the categorie s in the catalog to see the cores you need. follow the steps below to instantiate, configure, and connect th e components in the design: 1. drag and drop a coreabc instance onto the canvas. on the parameters tab of the coreabc configuration window, most of the settings ca n be left at their default va lues apart from these changes: ?set data bus width to 16 ?set number of i/o inputs to 16 ?set number of i/o outputs to 16 ?set interrupt support to active high. 2. on the program tab of the configuration window, enter the program shown in the screen shot in figure 9-5 on page 59 and then click the ok button to dismiss the co reabc configuration window. figure 9-4 ? name the smartdesign component
instantiate, configure, and connect the components 59 3. drag and drop coreapb3 onto the smartdesign canvas. accept the default configuration by clicking ok on the coreapb3 configuration window. note that th e apb slot size settings should always match for coreabc and coreapb3. this sett ing has a default value of 256 locations on both cores. 4. drag and drop coretimer onto the smartdesign canvas. in the coretimer configuration window, set the width option to 16 bit and leave the interrupt active leve l as high and click ok . 5. choose smartdesign > auto connect (or right-click on a blank area of the canvas and select auto connect). a window entitled modi fy memory map will appear, which provides the opportunity to move figure 9-5 ? program tab
example design using coreabc 60 the timer peripheral to a different slot on the apb3 bu s. accept the default (slo t 0) location by clicking the ok button. auto connect will connect the clock, reset, a nd bus connections. some manual connections must be made as follows. click on the timint pin of coretimer and, while holding the ctrl key down on the keyboard, click on the intreq pin of coreabc. right-click on either of these highlighted pins and select connect to connect the two pins t ogether. right-click on the io_out [15:0] pin of coreabc and select promote to top level to connect the outputs to the top level. next click again on the io_out [15:0] pin of coreabc and, while hol ding down the ctrl key, also click on the io_in [15:0] pin of coreabc. then right-click on either of thes e highlighted pins and select connect to loop the general purpose outputs back to the ge neral purpose inputs. fina lly, right-click on each of the unconnected ports and select mark unused (the unconnected ports are intact on coreabc and ports s1 to s15 on coreapb3). an x will appear at the end of the open wire connected to each port marked as unused. the design should re semble the one shown in figure 9-6 . . 6. choose smartdesign > generate design (or right-click on a blank ar ea of the canvas and select generate design ) to generate the design. if you have omitted marking unconnected ports as unused, an information window mentioning warnings will pop up. if there are any warnings, choose smartdesign > check design rules and review the warnings. system simulation before running a simulation of the system, we will adjust some of the simulation options. 1. in the project flow window, right-click on the simulation (modelsim ? ) button and select options . a project settings window will appear , with the simulation tab selected. in the left pane visible in the figure 9-6 ? coreabc design
system simulation 61 simulation tab, click on do file under modelsim options. in the right pane set the simulation runtime to 100 s, shown in figure 9-7 . 2. in the left pane, click on waveforms under modelsim options and in the right pane click the check box to select log all signals in the design, as shown in figure 9-8 on page 62 . logging all signals allows signals to be added to the waveform vi ewer in the simulator after the simulation has completed. for a large design and/ or a long simulation run time, it is probably better first to run a short simulation and then add the signals of interest to th e waveform viewer. the wave form format would then be saved to a do file (typi cally named wave.do) and, in the wave forms options window, you would click the figure 9-7 ? project settings ? simulation time
example design using coreabc 62 include do file option and enter the a ppropriate filename for the included do file value. the log all signals in the design option would be deselected. 3. click the ok button to dismiss the window. 4. back in the project flow window, click the simulation (modelsim) button to launch the simulation. the simulator will launch and run and, by default, all testbe nch signals will be di splayed in the waveform viewer. the testbench automatically create d for this design, when the desi gn was generated in smartdesign, contains only clock and reset signa ls and these are displayed in th e modelsim wave window (waveform viewer) with their exact names of sysclk and ns ysreset. the io_out output from coreabc is also of interest in this design. we should be able to observe the moving 1 pattern on this port. 5. to view io_out in the wave window, click on the abc_system instance name (which should be abc_system_0 by default) in the simulation window. after doing this, the objects window will list all of the signals present in abc_system. scroll to the io_out signal in the objects window and drag and drop this onto the wave window. it should be possible to observe the moving 1 pattern on the io_out trace. it may figure 9-8 ? simulation settings
system simulation 63 be easier to see the pattern by viewing io_out in hexadecimal form. to do this, right-click the io_out signal in the wave window and select radix > hexadecimal . figure 9-9 illustrates what should be observed when io_out is disp layed as a hexadecimal signal. figure 9-9 ? modelsim simulation showing io_out waveform
example design using coreabc 64 simulation of coreabc only (unit test) as well as running a system simulation, it is also possible to run a unit test on coreabc only. to do this, ensure that the testbench configuration option fo r coreabc is set to user (which is the default setting) before generating the design in smartdesign. in the hier archy tab of the design explorer window of project manager, browse to the coreabc instance. right-click on the instance and select set as root, as illustrated in figure 9-10 . with the coreabc instance set as the design root, click the simulation button. modelsim will launch and automatically run the coreabc unit te stbench. a "tests complete ? okay" type message wi ll be displayed in the modelsim transcript window on successful completion of the test bench, as shown in figure 9-11 on page 65 . figure 9-10 ? set as root
simulation of coreabc only (unit test) 65 figure 9-11 ? modelsim simulation window
example design using coreabc 66 synthesis to synthesize the design, firs t ensure that the design root is set to the top level of the design, which is abc_system. the design root may have changed if, for example, you ran a core abc unit test as described in the "simulation of coreabc only (unit test )" section on page 64 . click the synthesis button in the project flow window to launch the synplify synthesi s tool. click run to run synthesis. place-and-route to run place-and-route, click the place&route button in the project flow win dow to launch the designer tool. some dialog windows will be displaye d as designer starts. enter appropr iate information in these windows? normally the default entries ca n be accepted by clicking the ok button on each window. in designer, click the compile button to run the compile stage. if you intend to implement the design on a real board, you will need to make some pin assignments to suit th e target board. one way of doing this is to use the i/o attribute editor (by clicking on the button of the same na me) after compile has completed. afte r compiling and making any necessary pin assignments, click the layout button to run the layout stage. after layout has completed, a programming file can be created by clicking the programming file button and clicking ok to the subsequent windows which pop up after making any necessary edits to th e information presented in these windows.
67 10 ? coreabc v2.3 migration guide migrating an existing design which uses coreabc v2.3 to one which uses coreabc v3.0 involves a number of steps. coreabc v2.3 required the corecons ole tool to either create a complete coreabc based design or to create a coreabc component (essentially a wrapped coreabc in stance) which would typicall y be instantiated in a smartdesign design. coreabc v3.0 can be instantiated natively in a smartdes ign design and doe s not require the coreconsole tool at all. a key difference to be aware of be tween coreabc v2.3 and coreabc v3.0 is that the coreabc v2.3 is designed for use with coreapb whereas coreabc v3.0 must be used with coreapb3. follow these steps to migrate a design us ing coreabc v2.3 to one using coreabc v3.0: 1. open the original coreabc v2.3 based design in coreconsole. 2. note/record the coreabc conf iguration settings and make a copy of the program code. 3. delete the coreabc instance from the design. 4. save and generate th e design minus the corea bc instance. it may be necessary to make some stitching/connection change s at this point to allo w the design to be generated without the coreabc instance in place. for example, you may need to tie off some inputs to other co res which were previously driven by outputs from coreabc. 5. import the generated design into libero ide / smartd esign and, when prompted, allow the tool to convert the design from a coreconsole de sign to a smartdesign design. 6. open the smartdesign design. 7. if in the original design coreabc v2.3 was used to master coreapb, replace coreapb with coreapb3. 8. instantiate coreabc v3.0 and apply the original configurat ions and program code from step 2 . 9. connect and generate the design.

69 a ? example instruction sequence the following shows an example instruction sequence that uses coreabc to control co reai, to detect whether a voltage source is within a range. // sample code that reads an analog input and sets an output depending on a threshold def acm_size 90 def adc_stat_hi_addr 0x11 def acm_ctrlstat 0x0 def acm_data_addr 0x04 def acm_addr_addr 0x02 def adc_ctrl2_hi_addr 0x09 // set up uart and put out welcome 115200 baud assuming 50 mhz clock $reset apbwrt dat8 1 8 27 apbwrt dat8 1 12 1 $welcomemessage wait until input0 apbwrt dat8 1 0 'o' wait until input0 apbwrt dat8 1 0 'k' wait until input0 apbwrt dat8 1 0 10 wait until input0 apbwrt dat8 1 0 13 // set up core ai // reset acm wait while input1 apbwrt dat8 0 acm_ctrlstat 1 wait while input1 // wait until calibrated $waitcalibrate apbread 0 adc_stat_hi_addr and 0x8000 jump ifnot zero $waitcalibrate // program av, ac, at, ag registers load 0 $waitregprog wait while input1 apbwrt acc 0 acm_addr_addr apbwrt acm 0 acm_data_addr add 1 cmp acm_size jump ifnot zero $waitregprog // wait for adc calibrated wait while input1 iowrt 1 // now get the pot value, which is on ac5 = ch17 0x11 // also mask bits $mainloop apbwrt dat16 0 adc_ctrl2_hi_addr 0x1100 wait while input0 apbread 0 adc_stat_hi_addr and 0x0fff
example instruction sequence 70 // got the value in the accumalator, store in ram in 1 mv value shl0 shl0 ramwrt 0 // now generate bcd value load 0 ramwrt 11 ramwrt 12 ramwrt 13 // 0 = value; 11-14 is bcd value $bcd1 sub 1000 jump if negative $bcd2 push ramread 11 inc ramwrt 11 pop jump $bcd1 $bcd2 add 1000 $bcd3 sub 100 jump if negative $bcd4 push ramread 12 inc ramwrt 12 pop jump $bcd3 $bcd4 add 100 $bcd5 sub 10 jump if negative $bcd6 push ramread 13 inc ramwrt 13 pop jump $bcd5 $bcd6 add 10 ramwrt 14 // bcd value is now in memory; send to uart $valuetouart wait until input0 ramread 14 add 0x30 apbwrt acc 1 0 wait until input0 apbwrt dat8 1 0 '.' wait until input0 ramread 13 add 0x30 apbwrt acc 1 0 wait until input0 ramread 12 add 0x30 apbwrt acc 1 0 wait until input0 ramread 11 add 0x30 apbwrt acc 1 0
71 wait until input0 apbwrt dat8 1 0 'v' wait until input0 apbwrt dat8 0 0 10 wait until input0 apbwrt dat8 0 0 13 jump $mainloop this sequence allows coreabc to ini tialize coreai and then sample an adc channel, converting the value to bcd (binary coded decimal) and transmitting the value using coreuart. in this case, the busy output from coreai is connected to the io_in(0) input of coreabc.

73 b ? instruction summary this section detail s all the coreabc instructions . the encoding can be found in table b-1 on page 88 . instructions nop operation no operation flags unchanged clock cycles 3 load dat data operation load accumulator with immediate data value. flags zero: set if value is zero. negative: set if value is negative. clock cycles 3 load ram address operation load accumulator with ram location. flags zero: set if value is zero. negative: set if value is negative. clock cycles 3
instruction summary 74 inc operation increment the accumulator. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 and dat data operation and the accumulator with th e immediate data value. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 and ram address operation and the accumulator w ith the ram location. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 or dat data operation or the accumulator with the immediate data value. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3
instructions 75 or ram address operation or the accumulator with the ram location. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 xor dat data operation xor the accumulator with the immediate data value. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 xor ram address operation xor the accumulator with the ram location. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 add dat data operation add the immediate data va lue to the accumulator. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3
instruction summary 76 add ram address operation add the ram location to the accumulator. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 sub dat data operation subtract the immediate data value from the accumulator. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 shl0 operation shift the accumulator left; lsb <= 0. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 shr0 operation shift the accumulator right; msb <= 0. flags zero: set if resultant value is zero. negative: set if resultant value is negative ( not set ). clock cycles 3
instructions 77 shl1 operation shift the accumulator left; lsb <= 1. flags zero: set if resultant value is zero ( not set ). negative: set if resultant value is negative. clock cycles 3 shr1 operation shift the accumulator right; msb <= 1. flags zero: set if resultant value is zero ( not set ). negative: set if resultant value is negative ( set ). clock cycles 3 shle operation shift the accumulator left; lsb <= lsb. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 shre operation shift the accumulator right; msb <= msb. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3
instruction summary 78 rol operation rotate the accumulator left; lsb <= msb. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 ror operation rotate the accumulator right; msb <= lsb. flags zero: set if resultant value is zero. negative: set if resultant value is negative. clock cycles 3 cmp dat data operation compare the accumulator with the imme diate data value. uses boolean and. flags zero: set if values are equal. negative: set if both msbs are set. clock cycles 3 cmp ram address operation compare the accumulator with th e ram location. uses boolean and. flags zero: set if values are equal. negative: set if both msbs are set. clock cycles 3
instructions 79 cmpleq dat data operation compare the accumulator with the immediate data value. uses subtract operation. flags zero: set if values are equal. negative: set if accumulator is less than the data value. clock cycles 3 bitclr n operation clear accumulator bit n. uses boolean and. flags zero: set if resultant accumulator value is zero. negative: set if resultant accumulator value is negative. clock cycles 3 bitset n operation set accumulator bit n. uses boolean or. flags zero: set if resultant accumulator value is zero (not set ). negative: set if resultant accumulator value is negative. clock cycles 3 bittst n operation tests accumulator bit n. uses boolean and. flags zero: set if the bit is zero. negative: undefined clock cycles 3
instruction summary 80 apbread slot address operation reads the apb from the specified slot and address, and stores the value in the accumulator. flags unchanged clock cycles 5 plus any additional cycles caused by pready apbwrt acc slot address operation writes the accumulator to the apb at the specified slot and address. flags unchanged clock cycles 5 plus any additional cycles caused by pready apbwrt acm slot address operation writes the value in the acm table indexed by the accumulator to the apb at the specified slot and address. flags unchanged clock cycles 5 plus any additional cycles caused by pready apbwrt dat slot address data operation writes the data value to the apb at the specified slot and address. flags unchanged clock cycles 5 plus any additional cycles caused by pready apbwrt dat8 slot address data operation writes only the lowest eight bits of the data value to the apb at the sp ecified slot and a ddress. specifying dat8 rather than dat may reduce tile count when ahb_dwidth ? 16. flags unchanged clock cycles 5 plus any additional cycles caused by pready
instructions 81 apbwrt dat16 slot address data operation writes only the lowest 16 bits of th e data value to the apb at the specif ied slot and address. specifying dat16 rather than dat may reduce tile count when ahb_dwidth = 32. flags unchanged clock cycles 5 plus any additional cycles caused by pready apbreadz slot operation reads the apb from the specified slot and address, and stores the value in the accumulator. the z register is used as the apb address. flags unchanged clock cycles 5 plus any additional cycles caused by pready apbwrtz acc slot operation writes the accumulator to the apb at the specified slot and address. the z register is used as the apb address. flags unchanged clock cycles 5 plus any additional cycles caused by pready apbwrtz acm slot operation writes the value in the acm table indexed by the accumulator to the apb at the specified slot and address. the z register is used as the apb address. flags unchanged clock cycles 5 plus any additional cycles caused by pready
instruction summary 82 apbwrtz dat slot data operation writes the data value to the apb at the specified slot and address. the z register is used as the apb address. flags unchanged clock cycles 5 plus any additional cycles caused by pready apbwrtz dat8 slot data operation writes only the lowest eight bits of th e data value to the apb at the slot a nd address pointed to by the z register. specifying dat8 rather than dat ma y reduce tile count when ahb_dwidth ? 16. the z register is used as the apb address. flags unchanged clock cycles 5 plus any additional cycles caused by pready apbwrtz dat16 slot data operation writes only the lowest 16 bits of th e data value to the apb at the specif ied slot and address. specifying dat16 rather than dat may reduce tile c ount when ahb_dwidth = 32. the z regi ster is used as the apb address. flags unchanged clock cycles 5 plus any additional cycles caused by pready loadz dat data operation loads the z register wi th immediate data value. flags zzero: set if value is zero. clock cycles 3
instructions 83 decz operation decrements the z register. flags zzero: set if the z register decrements to zero. clock cycles 3 incz operation increments the z register. flags zzero: set if the z register increments to zero. clock cycles 3 addz data operation adds data to the z register. flags zzero: set if the resultant z register value is zero. clock cycles 3 ioread operation load the io_in port value into the accumulator. flags updated clock cycles 3 iowrt dat data operation writes the data value to the i/o register that drives the io_out top-level port. flags unchanged clock cycles 3
instruction summary 84 iowrt acc operation writes the accumulator to the i/o register that drives the io_out top-level port. flags unchanged clock cycles 3 ramread address operation loads the accumulator with the value stored at the specified address in the internal memory. flags zero: set if read value is zero. negative: set if read value is negative. clock cycles 3 ramwrt acc address operation writes the accumulator to the specified address in the internal memory. flags unchanged clock cycles 3 ramwrt dat address data operation writes the data value to the specified address in the internal memory. flags unchanged clock cycles 3
instructions 85 pop operation decrements the stack pointer and then loads the accumulator with the internal memory location addressed by the stack pointer. flags zero: set if read value is zero. negative: set if read value is negative. clock cycles 3 push dat data operation writes the immediate data to the internal memory loca tion addressed by the stack pointer and then decrements the stack pointer. flags unchanged clock cycles 3 push acc operation writes the accumulator to the internal memory location addressed by the stack pointer and then decrements the stack pointer. flags unchanged clock cycles 3 jump address operation jumps always to specified instruction address. flags unchanged clock cycles 3
instruction summary 86 jump if|ifnot condition address operation jumps on or not on condition to specified instru ction address. conditio ns are specified in table b-1 on page 88 . flags unchanged clock cycles 3 call address operation jumps always to specified instruction address. the fo llowing instruction address is pushed onto the stack and the stack pointer decremented. flags unchanged clock cycles 3 call if|ifnot condition address operation jumps on or not on condition to specified instruction addr ess. the following instruct ion address is pushed onto the stack and the stack pointer decrem ented. conditions are specified in table b-1 on page 88 . flags unchanged clock cycles 3 return operation jumps to the instruction address read from th e stack. the stack pointer is incremented. flags unchanged clock cycles 3
instructions 87 return if|ifnot condition operation jumps on or not on condition to the instruction address re ad from the stack. the stack pointer is incremented. conditions are specified in table b-1 on page 88 . flags unchanged clock cycles 3 retisr operation jumps to the instruction address read from the stack. the stack pointer is increm ented. the intact output is deactivated. flags restored to the values preceding the interrupt. clock cycles 3 return if|ifnot condition operation jumps on or not on condition to the instruction address re ad from the stack. the stack pointer is incremented. the internal intact output is deacti vated. conditions are specified below. flags restored to the values preceding the interrupt. clock cycles 3 wait until|while condition operation wait at the current instruction until or while a condition is true. conditions are specified below. flags unchanged clock cycles 3 to ?
instruction summary 88 halt operation halt flags unchanged clock cycles ? condition codes the conditions codes are shown in table b-1 . table b-1 ? condition codes condition description always always zero accumulator zero negative accumulator negative zzero z register zero input0 input0 set input1 input1 set and similarly for higher inputs, if available positive equivalent to not negative lte_zero less than or equal to zero; the combination negative or zero gt_zero greater than zero; the co mbination not (negative or zero)
89 c ? list of document changes the following table lists critical changes that we re made in the current version of the document. previous version changes in current version (50200085-4) page 50200085-3 (january 2008) the "coreabc overview" section was revised. iglooe, igloo plus, and proasic plus were added to the "supported device fa milies" section . the core version was revised to v3.0. 5 , 6 the "supported interfaces" section and "utilization and performance" section were revised. the values in the utilizat ion tables were updated. 6 the "internal architecture" chapter was revised, in cluding deletion of the " advanced peripheral bus " and " soft configuration?ram-based operation " sections. figure 1-1 ? coreabc block diagram was replaced. 11 the "tool flows" section was significantly revi sed. smartdesign has replaced coreconsole. 13 the description of interf aces was revised in the "coreabc interfaces" section . table 3-1 ? coreabc parameters and table 3-6 ? coreabc port descriptions were revised, including the addition of new parameters and revision of existing parameters. 15 , 19 the "address spaces" section and "registers" section were updated. new columns, flags and cycles, were added to the tables in the "instruction set" section and two new instructions were added to table 4-1 ? the boolean and arithmetic instruction group . 21 through 26 the "coreabc operation" chapter was revised extensively. 27 the "coreabc configuration" chapter was revised extens ively, including replacing figure 6-1 ? configuration parameters and figure 6-3 ? coreabc c onfiguration validation . a number of parameters were deleted and added. 29 the "coreabc programming" chapter was replaced. 35 the " adding user instructions " chapter was deleted. n/a the "testbench and simulation" chapter was replaced. 53 the "example design using coreabc" and "coreabc v2.3 migration guide" chapters are new. 55 , 67 the following operations were deleted from the "instruction summary" chapter: sub ram address cmpleq ram address loadz ram address 73 50200085-2 the "supported device families" section was added. 6 a note regarding frequency of igloo devices was added to table 1 ? coreabc utilization data (hard mode?instructi ons held in tiles) and table 2 ? coreabc utiliza tion data (soft mode? instructions held in ram) . 6 , 9 the ?fusion, proasic3/e, proasic3l, axcelerator, and rtax-s families? section was updated to include proasic3l. 13
list of document changes 90 50200085-1 supported core version updated in "core version" section. 6 supported version of libero ide updated in "supported tool flows" section. 6 the loadloop register was renamed z regist er. the loadz condition flag was renamed zzero. n/a table 1 ? coreabc utilization data (har d mode?instructions held in tiles) replaced and table 2 ? coreabc utilization data (soft mode?instructions held in ram) created. 6 "utilization and performance" section updated. 6 figure 1-1 ? coreabc block diagram updated. 11 eq 1-2 and eq 1-4 updated. 13 figure 2-1 ? coreabc configuration screen updated. 16 the "simulation flows" section was updated. 13 table 3-1 updated, with numerous parameter changes, a dditions, and deletions. 19 the "en_datam parameter" section was added. 18 "internal data ram address space (optional)" and "i/o address space" sections updated. 21 the ?instruction set? section was replaced. 26 table 5-1 ? coreabc instruction encoding updated variously. 25 "simulation logging" section updated. 28 figure 6-1 ? configuration parameters and figure 6-3 ? coreabc configuration validation were updated. 29 , 33 "number of i/o inputs" section added and "number of i/o flag inputs" section modified. 30 "alu operation from memory" , "apb indirect addressing" , and "supported data sources" sections added. 31 figure 7-1 ? coreabc programming screen and figure 7-2 ? vhdl analysis were updated. 35 , 36 "verification tests" section updated. 42 ?example instruction sequence? appendix modified. 49 many instructions were added or changed in the "instruction summary" section . 73 50200085-1 the "core version" and "supported interfaces" sections are new. 6 values in the configuration column were updated in table 1 ? coreabc util ization data (hard mode?instructions held in tiles) . 6 the last paragraph was changed in the "acm lookup table for use with coreai" section. 27 the "automatically created memory image files" section is new. 38 the "updating the program and flash memory contents" section is new. 39 the "instruction summary" section is new. 73 previous version changes in current version (50200085-4) page
91 d ? product support actel backs its products with various support services including customer se rvice, a customer technical support center, a web site, an ftp site, electronic mail, and worl dwide sales offices. this a ppendix contains information about contacting ac tel and using thes e support services. customer service contact customer service for non-tec hnical product support, such as produc t pricing, product upgrades, update information, order stat us, and authorization. from northeast and nort h central u.s.a., call 650.318.4480 from southeast and s outhwest u.s.a., call 650. 318.4480 from south cent ral u.s.a., call 650.318.4434 from northwest u.s.a., call 650.318.4434 from canada, call 650.318.4480 from europe, call 650.318.4252 or +44 (0) 1276 401 500 from japan, call 650.318.4743 from the rest of the world, call 650.318.4743 fax, from anywhere in the world 650.318.8044 actel customer technical support center actel staffs its customer technical support center with highly skil led engineers who can help answer your hardware, software, and desi gn questions. the customer technical suppor t center spends a great deal of time creating application notes and answers to faqs. so, before you c ontact us, please visit our online resources. it is very likely we have alread y answered your questions. actel technical support visit the actel customer support website ( www.actel.com/support/se arch/default.aspx ) for more information and support. many answers available on the se archable web resource include diagra ms, illustrations, and links to other resources on the actel web site. website you can browse a variety of te chnical and non-technical inform ation on actel?s home page, at www.actel.com . contacting the customer technical support center highly skilled engineers staff the te chnical support center from 7:00 a.m. to 6:00 p.m., pacific time, monday through friday. several ways of contacting the center follow: email you can communicate your tec hnical questions to our email address and receive an swers back by email, fax, or phone. also, if you have design problems, you can email your design files to receive assistance. we constantly monitor the email account throughout the day. when sending your request to us, please be sure to include your full name, company name, and your c ontact information for efficient processing of your request. the technical suppor t email address is tech@actel.com .
product support 92 phone our technical support center answers al l calls. the center retrieves inform ation, such as your name, company name, phone number and your question, and then issues a case number. the center then forwards the information to a queue where the first available a pplication engineer receives the data and returns your call. the phone hours are from 7:00 a.m. to 6:00 p.m., paci fic time, monday through friday. th e technical support numbers are: 650.318.4460 800.262.1060 customers needing assistance outside the us time zones can either contact technical support via email (tech@actel.com) or c ontact a local sales of fice. sales office li stings can be found at www.actel.com/company/ contact/default.aspx .
93 index a acm lookup 27 actel electronic mail 91 telephone 92 web-based technical support 91 website 91 address spaces 21 alu 11 analysis 36 apb interface 6 apb slave interface address map 52 b block diagram 11 c configuration parameters 30 contacting actel electronic mail 91 telephone 92 web-based technical support 91 coreabc block diagram 11 inputs 19 overview 5 programmer?s model 21 typical system 5 cross validation of configuration fields 32 e example design 55 f flags 11 h hard mode 36 hexadecimal si gnal display 63 i instantiate components 58 instruction memory, access to 51 instruction modes 36 instruction set 22 internal architecture 11 interrupt operation 27 l libero ide place-and-route in 14 synthesis in 13 log signals 61 m manual connections, example 60 migration from v2.3 67 modelsim 62 transcript window 65 n nvm mode 43 o obfuscated 13 p place-and-route 66 ports 19 product support 92 electronic mail 91 technical support 91 telephone 92 website 91 r rotating 1 55 rtl 13 s soft mode 36 stack 27 synthesis 66 system simulation, example 60 t technical support 91 testbench operation 53 u unit test 64 utilization data 6 , 9 w web-based technical support 91
50200085-5/9.10 actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. river court,mea dows business park station approach, blackwater camberley surrey gu17 9ab united kingdom phone +44 (0) 1276 609 300 fax +44 (0) 1276 607 540 actel japan exos ebisu buillding 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 http://jp.actel.com actel hong kong room 2107, china resources building 26 harbour road wanchai, hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com.cn actel is the leader in low-power fpgas and mixed-signal fpgas a nd offers the most comprehensive portfolio of system and power management solutions. power matte rs. learn more at www.actel.com. ? 2010 actel corporation. a ll rights reserved. actel, actel fusion, igloo, libe ro, pigeon point, proasic, smartfusion and the a ssociated logos are trademarks or registered trademarks of actel corporation. all other trademarks and service marks are the property of their resp ective owners.

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